In fabricating large application specific integrated circuits ("ASICs"), it is common practice to design the ASIC as a series of sub-sections whose nodes are interconnected with wide buses. If interconnecting requires, say 16 bits, the integrated circuit ("IC") chip may contain sixteen 1-bit wide buses, with enabling or arbitration signals determining the source of the bit coupled to the one-bit bus. The buses are low resistivity metal traces, sized to accommodate the current flow associated with the signals carried across the bus.
FIG. 1 depicts a prior art configuration wherein data are coupled to or from a one-bit bus 2 on an integrated circuit chip 4 using tristate buffer modules, 6-0, 6-1, 6-2, 6-3 (although more or less than four buffer modules may instead be used). Each buffer module defines an input/output node ("I/O") that may be coupled to one or more sub-sections or circuits on IC chip 4 by assertion of an appropriate enabling arbitration select signal.
Each buffer module has an input port, an enabling or arbitration port and an output port. For example, buffer 6-0 has an input port coupled to receive an I/O signal Dout0 from elsewhere on IC chip 4. Buffer 6-0 has an enabling port coupled to receive an output enabling or arbitration signal ARB-0, and also has an output port coupled to deliver a signal Din0. In common tristate buffer fashion, the signal Din0 will replicate the signal Dout0 only when ARB-0 is in an enabling state. In this fashion the sub-section circuit generating Dout0 can communicate one-bit of this signal across bus 2 to some other sub-section circuit also coupleable to bus 2.
If I/O signal Dout0 is to be coupled to bus 2, ARB-0 will be in an enabling state permitting buffer 6-0 to output a replica of signal Dout0. By contrast, enabling signals ARB-1, ARB-2, ARB-3 would each be in a disabling state that precluded respective buffers 6-1, 6-2, 6-3 from outputting a signal to bus 2. Only one ARB signal is to be in the enabling state at a time, which means that only one tristate buffer module is selected at any given time for coupling Dout signals to bus 2.
In the manner described, the buffer modules serve as mechanisms for coupling signals between the buffer I/O node and bus 2, the coupling being determined by the enabling ARB signals.
It is understood that if the bus is N-bits wide, there will be N buses 2, and N groups of buffers 6, each buffer having an input port, an arbitration port, and an output port. Using FIG. 1 as an example, an IC requiring a 16-bit wide bus would replicate the structure of FIG. 1 sixteen times. There would be sixteen bus 2 structures and 64 (e.g., 16.times.4) buffer modules 6, one such structure being present for each bit-position in the bus. However, each group of sixteen buffer modules would be coupled to the same ARB signal, with the four ARB signals thus each being coupled to blocks of sixteen buffer modules.
FIG. 2A shows a typical implementation of a tristate buffer, e.g., buffer 6-0, which typically operate from an upper power supply Vdd and a lower power supply Vss that is often ground. At its input port, buffer 6-0 receives Dout0, and at its output port outputs Din0, providing the ARB-0 enabling signal is present (e.g., is a digital "1"). Depending upon the circuit design, Din0 may replicate or be an inverted version of Dout0, and buffer 6-0 may enable when ARB-0 is a digital "0".
The output of buffer 6-0 is shown coupled to a load impedance Z.sub.L that may be represented generally by a resistance R.sub.L shunted by an effective capacitive load C.sub.L. Load impedance Z.sub.L represents the load seen by the buffer output. As will be described later, Z.sub.L includes load contributions from the bus, from the three other buffer modules, and from the Din0 port of buffer 6-0 itself.
As shown in FIG. 2A, buffer 6 may be implemented with bipolar transistors, complementary metal-on-semiconductor ("CMOS") transistors, or a combination of each ("BiCMOS"). Buffer 6 typically will include two inverters I1 (here a NAND gate) and I2 coupled in series, or I3 (here a NOR gate) and I2 coupled in series. The output of the first inverter is presented as input to the second inverter, and the output of the second inverter is the buffer output, which has the same phase as the input to the first inverter.
In the CMOS implementation of FIG. 2A, each inverter comprises a P-type pull-up metal-on-semiconductor ("PMOS") transistor and an N-type MOS ("NMOS") transistor coupled in series between Vdd and Vss. For example, I1 may comprise a PMOS transistor P1 (not shown) and an NMOS transistor N1 (not shown), I2 comprises PMOS transistor P2 and NMOS transistor N2, and I3 comprises transistors P3, N3 (not shown). Because I2 drives a relatively large load, output transistors P2 and N2 will generally be larger sized devices than the transistors comprising I1 or I3.
The arbitration or enabling function may be implemented using the NAND gate (I1), INVERTER and NOR gate (I3) logic shown, or using other techniques well known to those skilled in the relevant art.
When Dout0 is a digital "1", within I1 transistor P1 turns off and N1 turns on, and the first inverter output is a digital "0". Upon receipt of this "0", in the second inverter I2, P2 turns on, N2 turns off, and the signal Din0 will be a digital "1", and buffer 6-0 sources current into bus 2. When Dout0 is a digital "0", P1 turns on, N1 turns off, and the output from the first inverter is a "1". Upon receipt of this "1", P2 in the second inverter turns off, N2 turns on, signal Din0 is a "0", and buffer 6-0 sinks current from bus 2.
FIGS. 2B-1 through 2B-4 depict voltage and current waveforms associated with output buffer 6-0. For example, although Dout0 is "1" before time t.sub.0, it is only after the enabling ARB0 signal goes high that buffer 6-0 is enabled to provide the Din0 output signal. At time t.sub.1, Dout0 goes low and, since ARB-0 is still enabling buffer 6-0, the Din0 signal also goes low. In the Din0 waveform, the voltage waveform drawn in phantom represents the case of a relatively large load capacitance C.sub.L. When C.sub.L is not especially large, the output voltage waveform slews more rapidly, but can overshoot and undershoot as shown.
It is thus appreciated from the Din0 waveform that as C.sub.L increases, the output voltage slew rate (dV/dt) decreases. To compensate for this, it is necessary to implement buffer 6-0 with larger output inverter transistors that can source or sink more current (i). (Of course, this assumes that the IC containing buffer 6 has sufficient area whereon to fabricate larger transistors. ) The ability to compensate for a large C.sub.L by increasing output buffer current follows from the equation: EQU i=C.sub.L .DELTA.V/.DELTA.t
Although large current handling transistors can improve output voltage slewrate, a large current capability can be detrimental. In practice, buffer 6-0 will not function perfectly because the various pull-up and pull-down transistors do not change states in perfect synchronism. The output buffer current waveform depicts the total current i.sub.o flowing through buffer 6-0. The i.sub.o current waveform drawn in phantom represents total current drawn by the buffer when the various buffer transistors are themselves large devices, e.g., devices with a relatively large drain current.
Note from this waveform that current spikes occur when the buffer transistors change states, for example at times t.sub.0 and t.sub.1. These spikes are created because for a brief moment, the PMOS and NMOS transistors in each inverter are simultaneously on, thus presenting a low impedance current path between the Vdd and Vss power supplies. In addition, current spiking occurs because the load capacitance C.sub.L component of Z.sub.L is being charged toward Vdd or discharged toward Vss (depending upon the direction of the output state change).
Thus, the i.sub.o waveform in FIG. 2B-4 suggests that compensating for a large load capacitance C.sub.L by implementing buffer 6-0 with large current transistors will aggravate current spiking. Those skilled in the art will appreciate that the current spiking waveforms can contain many high frequency components that represent electromagnetic ("EM") and radio frequency ("RF") noise that can interfere with other signals implemented on the IC containing buffer 6, and with signals elsewhere in a system contain this IC.
It will be appreciated from the foregoing that the use of tristate buffers 6 presents many problems. Although the configuration of FIG. 1 is commonly used in fully customized integrated circuit chips, this configuration aggravates current spiking and the need for fabricating relatively wide bus 2 metal traces. In practice, the width of the bus 2 metal will be in the range of about 3 .mu.m. In some applications, having to provide a sufficiently wide metal bus trace may compromise the layout of other portions of the IC due to space considerations.
The configuration of FIG. 1 is not point-to-point in that each buffer module is always coupled to more than one other buffer module, e.g., to three other buffer modules. As will now be described, this causes each buffer to see a substantial load impedance Z.sub.L, with resultant degradation of signal voltage slewrate.
Assume for example that ARB-0 enables buffer 6-0, and that ARB-1, ARB-2, ARB-3 disable buffers 6-1, 6-2, 6-3. The load Z.sub.L seen by the enabled (e.g., turned-on) buffer 6-0 includes (a) the metal trace bus 2, (b) whatever is coupled to Din0, (c) the output impedance capacitance of each of the other three disabled (e.g., turned-off) buffers, and (d) the Din1, Din2, Din3 loads contributed by each of the other three input buffers. The resultant load is the metal trace load and seven buffer loads. Since the metal trace typically is equivalent to about twelve buffer loads, the turned-on buffer must drive approximately sixteen equivalent loads. One standard equivalent load is about 0.032 pF, which is to say that 31.3 standard equivalent loads represent approximately 1.0 pF.
Unfortunately, if the tristate buffers are to drive sixteen equivalent loads and still provide output Din signals having a sufficiently rapid voltage slewrate, the buffer current i.sub.o must be increased. This in turn requires larger-sized buffer transistors, and can increase current spiking and noise generation.
It is also apparent from FIG. 1 and FIG. 2A that no more than one output enabling ARB signal may be on (e.g., "1") at any time. Any overlap in time between enabling signals, or "arbitration contention", can cause one turned-on buffer to attempt to drive a very low impedance load that includes another turned-on buffer, and vice verse. The resultant high current flow will usually damage if not destroy IC 4.
Testing prior art tristate buffer configurations such as shown in FIG. 1 is extremely challenging, and generally cannot be accomplished using conventional automatic testing routines and equipment. It is very difficult for conventional testing routines to determine which of a group of tristate buffers is actually driving the bus at a given time. Further, conventional test routines cannot detect the occurrence of contention with any great certainty. Stated differently, to successfully test the configuration of FIG. 1, it is necessary to demonstrate that contention can never occur. The testing procedures and equipment necessary to demonstrate this are difficult to implement.
For example, although scanning test protocols are commonly used to rapidly test ICs, such routines cannot be used with tristate buffer configurations such as shown in FIG. 1. In such testing, the various flipflops within an IC are temporarily coupled together in a ring and known data patterns are passed through the ring. Unfortunately, when tristate buffers are present, random output drive signals become propagated through the ring, introducing uncertainty and, what is worse, contention into the test procedure.
To summarize, there is a need for an on-IC bus structure that avoids the contention and testing problems associated with prior art tristate buffer configurations. It should be possible to fabricate such a structure using IC and metal trace areas not exceeding what would be required to implement a tristate buffer bus configuration.
The present invention provides such a bus structure.